1. Field of the Invention
Embodiments of the present invention relate generally to a semiconductor memory device. More particularly, embodiments of the invention relate to a semiconductor memory device capable of performing a page mode operation.
A claim of priority is made to Korean Patent Application No. 2005-06838, filed on Jan. 25, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Semiconductor memory devices are commonly used to provide temporary and long term data storage in modern electronic equipment. Semiconductor memory devices can be roughly classified into two categories: volatile memory devices and non-volatile memory devices. In a volatile memory device, data disappears once the device loses power. Volatile memory devices include, for example, dynamic random access memory (DRAM), static random access memory (SRAM). In a non-volatile memory device, on the other hand, stored data is retained even when the power is cut off. Non-volatile memory devices include, for example, programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash memory.
Flash memories are currently among the more popular forms of non-volatile memory. Among other things, flash memories are popular because of their non-volatility, large storage capacity, durability, fast program/read times, and cost.
Flash memory devices can be broadly classified into two categories depending on the type of logic gate used in each memory cell. The two categories are NAND flash memories and NOR flash memories. Typically, NAND flash memories are used for mass data storage because they are more highly integrated, cheaper, and faster to program and erase, but slower to read than NOR flash memories. NOR flash memories, on the other hand, are generally used to store data that needs to be read faster, but requires relatively few updates, such as program code.
One common technique used to improve the average access time and power efficiency for semiconductor memories is a “page mode operation”. Page mode operations are operations of a semiconductor memory device performed while the device is in a “page mode”. For example, the semiconductor memory device can be programmed or read while in the page mode. Briefly, in a page mode operation, a page of data is read into a buffer and then subsequent operations (e.g., reading, programming) are performed to locations within the page. FIG. 1 shows a waveform timing diagram of a conventional page mode read operation. The timing diagram in FIG. 1 is disclosed in Korean Patent Application No. 1992-18440.
Referring to FIG. 1, a start address Ax[15:0] is input to a semiconductor memory device from an outside source. In a page mode operation, start address Ax[15:0] is divided into a normal address Ax[15:3] and a page address Ax[2:0].
During the page mode operation, normal address Ax[15:3] stays the same, but page address Ax[2:0] can change to output different data from within the same page. FIG. 1 shows a page mode operation where a page length is eight words and page address Ax[2:0] has three bits. The semiconductor memory device receives an output enable signal nOE to control the output of data from the semiconductor memory device in the page mode read operation.
A conventional semiconductor memory device capable of performing a page mode operation typically comprises a normal address transition detector (NATD) for detecting changes (or transitions) in the normal address and a page address transition detector (PATD) for detecting changes (or transitions) in the page address. Each of the address transition detectors generates a pulse when a page or normal address changes. The conventional semiconductor memory device typically generates a clock signal for output data using pulses output by an address transition detector.
Unfortunately, the PATD in the conventional semiconductor memory device detects all variations in the page address. For example, when any of the three bits in a page address Ax[2:0] varies, the variation is detected. Monitoring all three bits, however, lowers the performance of the semiconductor memory device.